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\title{Synthesis Approach of 2D Mesh Network Inter Communication (2D-2D) using Network on Chip}
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\begin{document}

             \author[1]{Prachi  Agarwal}

             \author[2]{Dr. Anil Kumar  Sharma}

             \author[3]{Adesh  Kumar}

             \affil[1]{  }

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\date{\small \em Received: 8 December 2012 Accepted: 4 January 2013 Published: 15 January 2013}

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\begin{abstract}
        


The solution for the multiprocessor system architecture is Application specific Network on Chip (NOC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NOC can beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. The paper emphasizes on the network on chip modeling and synthesis of 2D network and intercommunication among multilevel 2D networks. NOC synthesis environment provides transaction level network modeling and address all the requirements together in an integrated chip. In the paper consideration is done for 2D, 8 x 8 network and similar networks are considered which are identified by their specific network address. NOC chip is developed using VHDL programming language. Design is implemented in Xilinx 14.2 VHDL software, functional simulation is carried out in Modelsim 10.1 b, student edition and synthesis process is carried out on Digilent Sparten -3E FPGA.

\end{abstract}


\keywords{network on chip (NOC), very high speed integrated circuit hardware description language (VHDL), field programmable gate array (FPGA), application spec}

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\let\tabcellsep& 	 	 		 
\section[{Introduction}]{Introduction}\par
etwork on Chip (NoC) \hyperref[b0]{[1]} [2] \hyperref[b2]{[3]} is the latest approach to overcome the limitation of bus based communication network. NoC is a set of routers employed in a network, in which different nodes are inter connected with their cores can communicate with each others. In a network data comes in packets and sent to the destination with IP via routers and links \hyperref[b3]{[4]} . When a packet reaches its destination address, it means it is switched \hyperref[b4]{[5]} to the IP attached to the router. On-chip communications among different networks is possible using interconnection network topology \hyperref[b4]{[5]}  \hyperref[b5]{[6]}, switching, routing, queuing .flow control  {\ref [11]} and scheduling. Research can be done for n-dimensional topological structures network on chip design. The idea of NoC is derived from distributed computing and large scale computer networks. There are different routing techniques used in NOC design considerations to meet high throughput and cover time to market. Due to big constraints on hardware and memory resources utilization, the routing methods for NoC should be very simple.\par
According to the need of processors, NoC technology gives chip designer's flexibility in choosing the network topology, according to University of Bologna professor Luca Benini, founder of and scientific advisor for iNoCs, a start-up provider of on-chip interconnection technology. High degree of parallelism and pipelining increases  {\ref [8] [12]} the performance of the system because all the links in the network works simultaneously on different data packets \hyperref[b13]{[13]}. As the complexity of the system is increasing, NOC is the solution to enhance system performance in comparison to the previous technological architectures such as dedicated, wires, point to point, bridges and shared buses. The scalability of system and throughput \hyperref[b17]{[17]} [20] will increase because algorithms are designed in such a way that it offers higher degree of parallelism. For example, a mesh NoC topology \hyperref[b18]{[18]} can function with parallelism and thus is well-suited for multiprocessor SoCs, whose cores must run in parallel. Prototype NoCs by the Electronics and Information Technology Laboratory of the French Atomic Energy Commission's Faust, the Swedish Royal Institute of Technology's Nostrum, and the Technion-Israel Institute of Technology's QNoC work with a mesh topology. a) Tools Utilized Design and implementation of mesh network is carried out using Project Navigator ISE 14.2, Xilinx company. It is a tool used to design the IC and to view their RTL (Register Transfer Logic) schematic. Model Sim EE 10.1b student's edition is a tool of Mentor Graphics Company used for simulation and debugging the functionality. The chip implementation is done using VHDL programming language.\par
The paper is organized as follows: Section I presents the introduction and the tools utilized. Section II describes intercommunication among 2D (8 x 8) mesh networks. Section III describes the FPGA synthesis environment. Section IV describes the Result and Performance Evaluation. Section V presents the Device utilization and timing summary. Conclusion is presented in Section VI.  
\section[{Intercommunication among 2D Mesh Networks}]{Intercommunication among 2D Mesh Networks}\par
Intercommunication among 2D NOC networks can be understood using arbitration logic selection of networks \hyperref[b12]{[12]}. First understanding, how a 2D networks behaves, then focusing on the intercommunication among 2D networks. 2D NOC \hyperref[b12]{[12]} follows the cross link which allows addressing any node at any time  {\ref [11]}. A 2D mesh network is connecting multiple inputs to multiple outputs in a matrix form. The 2D NOC architecture is a m × n mesh of switches \hyperref[b11]{[10]} and resources are placed on the slots formed by the switches. For an m x n architecture there are m nodes on X axis and n nodes on Y axis respectively. Considering an 8 x 8 structure in which 64 nodes can perform intra communication. Node identification is based on the row address and column address \hyperref[b0]{[1]}. For example, if row address = 000 and column address = 101, node 6 (N 6 ) is identified. Similarly there is the possibility of identifying any node. Table \hyperref[tab_0]{1} list the possible node address generation scheme for 2D 8 x 8 structure.     Step 2 : reset = 0, same clk is used for synchronization and provide rising edge.\par
Step 3 : Select the address of destination node Node\textunderscore address [5:0] of 6 bits for 8 x 8 structure.\par
Step 4 : Force the value of row\textunderscore address and column\textunderscore address of destination node. For 8 x 8 NOC row\textunderscore address[2:0] and column\textunderscore address[2:0] are of 3 bits.\par
Step 5 : Force the value of network address [1:0] of destination network. network\textunderscore address [1:0] = "00" for network 1, network\textunderscore address [1:0] = "01" for network 2, network\textunderscore address [1:0] = "10" for network 2 and network\textunderscore address [1:0] = "11" for network 3.\par
Step 6 : Give the eight bit value of data\textunderscore in. Force write\textunderscore en =1 and read\textunderscore en =0 and then run.\par
Step 7 :\par
Write\textunderscore en =0 and read\textunderscore en =1 and run. Desired output on destination is achieved.\par
When write\textunderscore en =1 and read\textunderscore en =0, the data is written in temp variable from the source node, when write\textunderscore en =0 and read\textunderscore en =1, the data is read from the temp variable to destination node. Clk is applied at the  Table  {\ref 3} : Design pins and their functional description for (8 x 8) NOC 
\section[{Pins}]{Pins}\par
Functional Description reset used for synchronization of the components by using clk clk Provide rising edge of clock pulse node\textunderscore address  {\ref [5:0]} Address of the source and destination node of 6 bits row\textunderscore address  {\ref [2:0]} represents address of the nodes in x direction (3 bits) column\textunderscore address [2:0] represents address of the nodes in y direction ( 3 bits) read\textunderscore en control signal to read data (1 bit) write\textunderscore en control signal to write data (1 bit) network\textunderscore address [1:0] Selection logic for the network ( 2 bits) data\textunderscore in  {\ref [7:0]} represents input data in the network (8 bits) data\textunderscore out  {\ref [7:0]} represents 8 bit output data of the destination node (8 bits)\par
IV. 
\section[{Synthesis}]{Synthesis}\par
The Spartan-3E starter kit  {\ref [21]} [22] provides easy way to test the various programs in the FPGA itself, by dumping the 'bit' file of the designed program in Xilinx software into the FPGA and then observing the output .The Spartan 3E FPGA board \hyperref[b8]{[8]} comes built in with many peripherals that help in the proper working of the board and also in interfacing the various signals to the board itself. Some of the peripherals included in the Spartan 3E FPGA board include: 2-line, 16-character LCD screen used for display the output, PS/2 mouse or keyboard port can be connected to the FPGA, VGA display port These switches are locked into FPGA using user constraint file (UCF). Figure  {\ref 6} shows the flow of inputs given to FPGA device. Four slide switches and four push-button switches are used to give the inputs to the FPGA board. They can also act as the reset switches for the various program Kit also has four-output, SPI-based on board Digital-to-Analog Converter (DAC) on board which is to be interfaced to give the analog output to the digital data values. Two-input, SPI-based \hyperref[b7]{[7]} [23] Analog-to-Digital Converter (ADC) with programmable gain preamplifier converts the real world analog signals into digital values.' Image processing inputs are given by the switches of kit and functionally tested on the corresponding LED's output.T he output data is flashed on LEDs. These LEDs are also locked in UCF file \hyperref[b16]{[16]}. The bit file of the program is burn out in The EPROM of FPGA and corresponding result is shown by blinking LEDs. The output can be shown on Digital storage oscilloscope (DSO). As shown in figure  {\ref 7}. The input data is 10101010, when reset switch = 0, no output is display on DSO. When reset switch =1, output data is 10101010.    \begin{figure}[htbp]
\noindent\textbf{2013}\includegraphics[]{image-2.png}
\caption{\label{fig_0}N © 2013}\end{figure}
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\noindent\textbf{1} \par 
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Row\tabcellsep \tabcellsep \tabcellsep \tabcellsep \multicolumn{2}{l}{Column Address}\tabcellsep \tabcellsep \tabcellsep \\
Address\tabcellsep 000\tabcellsep 001\tabcellsep 010\tabcellsep 011\tabcellsep 100\tabcellsep 101\tabcellsep 110\tabcellsep 111\\
000\tabcellsep n 1\tabcellsep N 2\tabcellsep N 3\tabcellsep N 4\tabcellsep N 5\tabcellsep N 6\tabcellsep N 7\tabcellsep N 8\\
001\tabcellsep N 9\tabcellsep N 10\tabcellsep N 11\tabcellsep N 12\tabcellsep N 13\tabcellsep N 14\tabcellsep N 15\tabcellsep N 16\\
010\tabcellsep N 17\tabcellsep N 18\tabcellsep N 19\tabcellsep N 20\tabcellsep N 21\tabcellsep N 22\tabcellsep N 23\tabcellsep N 24\\
011\tabcellsep N 25\tabcellsep N 26\tabcellsep N 27\tabcellsep N 28\tabcellsep N 29\tabcellsep N 30\tabcellsep N 31\tabcellsep N 32\\
100\tabcellsep N 33\tabcellsep N 34\tabcellsep N 35\tabcellsep N 36\tabcellsep N 37\tabcellsep N 38\tabcellsep N 39\tabcellsep N 40\\
101\tabcellsep N 41\tabcellsep N 42\tabcellsep N 43\tabcellsep N 44\tabcellsep N 45\tabcellsep N 46\tabcellsep N 47\tabcellsep N 48\\
110\tabcellsep N 49\tabcellsep N 50\tabcellsep N 51\tabcellsep N 52\tabcellsep N 53\tabcellsep N 54\tabcellsep N 55\tabcellsep N 56\\
111\tabcellsep N 57\tabcellsep N 58\tabcellsep N 59\tabcellsep N 60\tabcellsep N 61\tabcellsep N 62\tabcellsep N 63\tabcellsep N 64\end{longtable} \par
  {\small\itshape [Note: Network 1, network\textunderscore address is 01 Network 2, network\textunderscore address is 10 Network 3, and network\textunderscore address is 11 Network 4 is identified. It is also illustrated using figure3and table 2.]} 
\caption{\label{tab_0}Table 1 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{2} \par 
\begin{longtable}{P{0.36637931034482757\textwidth}P{0.4836206896551724\textwidth}}
Network\textunderscore Address\tabcellsep Selection Logic\\
00\tabcellsep Network 1 is selected\\
01\tabcellsep Network 2 is selected\\
10\tabcellsep Network 3 is selected\\
11\tabcellsep Network 4 is selected\\
\multicolumn{2}{l}{III. Result \& Performance Evaluation}\end{longtable} \par
 
\caption{\label{tab_1}Table 2 :}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5} \par 
\begin{longtable}{P{0.85\textwidth}}
and 6\end{longtable} \par
 
\caption{\label{tab_2}table 5}\end{figure}
 \begin{figure}[htbp]
\noindent\textbf{5} \par 
\begin{longtable}{P{0.6737403100775193\textwidth}P{0.01317829457364341\textwidth}P{0.01647286821705426\textwidth}P{0.06753875968992248\textwidth}P{0.03294573643410852\textwidth}P{0.046124031007751934\textwidth}}
\multicolumn{2}{l}{Logic Utilization}\tabcellsep \tabcellsep \multicolumn{3}{l}{Used Available Utilization}\\
Number of Slices\tabcellsep \tabcellsep \tabcellsep 335\tabcellsep 2448\tabcellsep 13 \%\\
\multicolumn{3}{l}{Number of Slice Flip Flops}\tabcellsep 80\tabcellsep 4896\tabcellsep 1 \%\\
\multicolumn{2}{l}{Number of 4 input LUTs}\tabcellsep \tabcellsep 653\tabcellsep 4896\tabcellsep 13 \%\\
\multicolumn{3}{l}{Number of bonded IOBs}\tabcellsep 31\tabcellsep 158\tabcellsep 19 \%\\
Number of GCLKs\tabcellsep \tabcellsep \tabcellsep 2\tabcellsep 24\tabcellsep 8 \%\\
\multicolumn{4}{l}{a) Timing Summary for 8 x 8 NOC}\tabcellsep \\
\multicolumn{6}{l}{Timing details provides the information of delay,}\\
\multicolumn{6}{l}{minimum period, minimum input arrival time before}\\
\multicolumn{6}{l}{clock and maximum output required time after clock [1].}\\
Speed Grade: -5\tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{6}{l}{Minimum Period : 4.937 ns (Maximum Frequency:}\\
202.536 MHz).\tabcellsep \tabcellsep \tabcellsep \tabcellsep \\
\multicolumn{2}{l}{VI.}\tabcellsep \multicolumn{3}{l}{Conclusion}\\
The\tabcellsep \multicolumn{2}{l}{hardware}\tabcellsep chip\tabcellsep for\tabcellsep 2D-2D\\
\multicolumn{4}{l}{intercommunication network is}\tabcellsep \end{longtable} \par
 
\caption{\label{tab_3}Table 5 :}\end{figure}
 			\footnote{© 2013 Global Journals Inc. (US)} 			\footnote{© 2013 Global Journals Inc. (US) Global Journal of Computer Science and Technology} 		 		\backmatter  			  				\begin{bibitemlist}{1}
\bibitem[Cong et al.]{b5}\label{b5} 	 		\textit{},  		 			Jason Cong 		,  		 			Yuhui Huang 		,  		 			Bo Yuan 		.  		Los Angeles Los Angeles, USA. p. .  		 			Computer Science Department University of California 		 	 
\bibitem[ The Research Bulletin of Jordan ACM]{b10}\label{b10} 	 		\textit{},  	 	 		\textit{The Research Bulletin of Jordan ACM}  		 2078-7952.  		II p. .  		 			Asymmetric Torus Network-on-Chip 		 	 	 (II) pp) 
\bibitem[Paulo and Ababei]{b17}\label{b17} 	 		‘3D Network-on Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans’.  		 			Vitorde Paulo 		,  		 			Cristinel Ababei 		.  	 	 		\textit{International Journal of Reconfigurable Computing}  		Hindawi Publishing Corporation. 2010.  	 	 (Article ID603059) 
\bibitem[A Network on Chip Simulator Sweden Master of Science Thesis in Electronic System Design (2002)]{b14}\label{b14} 	 		‘A Network on Chip Simulator’.  	 	 		\textit{Sweden Master of Science Thesis in Electronic System Design},  				Aug 2002. p. .  		 			Royal Institute of Technology 		 	 	 (Rikard Thid Thesis on) 
\bibitem[Bertozzi and Benini ()]{b3}\label{b3} 	 		‘A Network-on-Chip Architecture for Gigascale Systems-on-Chip, IEEE Circuits and systems magazine, second quarter’.  		 			Davide Bertozzi 		,  		 			Luca Benini 		.  	 	 		\textit{Xpipes}  		2004. p. .  	 
\bibitem[Nguyen and Dey (2002)]{b4}\label{b4} 	 		‘An interconnect architecture for networking systems on chips’.  		 			F 		,  		 			Karim A Nguyen 		,  		 			S Dey 		.  	 	 		\textit{IEEE Journal on Micro High Performance Interconnect}  		Sept 2002. 22  (5)  p. .  	 
\bibitem[Wang and Nurmi]{b20}\label{b20} 	 		\textit{Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network},  		 			Xin Wang 		,  		 			Jari Nurmi 		.  		Hindawi Publishing Corporation VLSI Design Volume2007. p. 18372.  	 	 (14 page) 
\bibitem[Borkar (1999)]{b15}\label{b15} 	 		‘design challenges of technology scaling’.  		 			S Borkar 		.  	 	 		\textit{IEEE Micro}  		July-August 1999.  (4)  p. 2329.  	 
\bibitem[Grot et al. ()]{b1}\label{b1} 	 		‘Express Cube Topologies for On-Chip Interconnects’.  		 			B Grot 		,  		 			J Hestness 		,  		 			S W Keckler 		,  		 			O Mutlu 		.  	 	 		\textit{15th International Symposium on Computer Architecture (HPCA)},  				2009.  	 
\bibitem[Agarwal et al. (2013)]{b0}\label{b0} 	 		‘Modeling and Simulation of 2D Mesh Topological Network on Chip (NOC)’.  		 			Prachi Agarwal 		,  		 			Anil Kumar Sharma 		,  		 			Adesh Kumar 		.  	 	 		\textit{International Journal of Computer Applications}  		June 2013. 72  (21)  p. .  	 
\bibitem[Mohammad Ayoub Khan]{b9}\label{b9} 	 		 			Mohammad Ayoub Khan 		.  		\textit{Abdul Quaiyum Ansari, A Quadrant-XYZ Routing Algorithm for},  				p. 3.  	 
\bibitem[Kumar et al.]{b12}\label{b12} 	 		‘Network on Chip for 3D Mesh Structure with Enhanced Security Algorithm in HDL Environment’.  		 			Adesh Kumar 		,  		 			Sonal Singhal 		,  		 			Piyush Kuchhal 		.  	 	 		\textit{International Journal of Computer Applications}  		IJCA. 59  (17)  p. .  	 
\bibitem[Atienzaa et al. ()]{b2}\label{b2} 	 		‘Network-on-Chip design and synthesis outlook’.  		 			David Atienzaa 		,  		 			Federico Angiolini 		,  		 			Srinivasan Murali 		,  		 			Antonio Pullinid 		,  		 			Luca Benini 		,  		 			Giovanni De Micheli 		.  	 	 		\textit{INTEGRATION, the VLSI journal Elsevier}  		2008. 41 p. .  	 
\bibitem[Lee et al. (2007)]{b8}\label{b8} 	 		‘On-chip communication architecture exploration: A quantitative evaluation of point-topoint, bus, and network-on-chip approaches’.  		 			H G Lee 		,  		 			N Chang 		,  		 			U Y Ogras 		,  		 			R Marculescu 		.  	 	 		\textit{ACM Trans. Des. Autom. Electron. Syst}  		Aug. 2007. 12  (3)  p. .  	 
\bibitem[Pratim Pande et al. ()]{b13}\label{b13} 	 		‘Performance evaluation and design trade-offs for network-on-chip interconnect architectures’.  		 			P Pratim Pande 		,  		 			C Grecu 		,  		 			M Jones 		,  		 			A Ivanov 		,  		 			R Saleh 		.  	 	 		\textit{IEEE Transactions on Computers}  		2005. 54  (8)  p. .  	 
\bibitem[Owens and Dally (2007)]{b7}\label{b7} 	 		‘Research challenges for on-chip inter connection networks’.  		 			J D Owens 		,  		 			W J Dally 		.  	 	 		\textit{IEEE MICRO}  		Oct. 2007. 27  (5)  p. .  	 
\bibitem[Semiconductor Complex Limited, Internet PDF: Data sheets of XC 95 series CPLD]{b16}\label{b16} 	 		\textit{Semiconductor Complex Limited, Internet PDF: Data sheets of XC 95 series CPLD},  		 	 
\bibitem[Wolf (2004)]{b18}\label{b18} 	 		‘The future of multiprocessor systems-onchips’.  		 			W Wolf 		.  	 	 		\textit{Proceedings of the 41 st Design Automation Conference (DAC'04)},  				 (the 41 st Design Automation Conference (DAC'04))  		June 2004. p. .  	 
\bibitem[Woo-Seo Ki1 et al. ()]{b19}\label{b19} 	 		\textit{The New Torus Network Design Based On 3-Dimensional Hypercube},  		 			Hyeong-Ok Woo-Seo Ki1 		,  		 			Jae-Cheol Lee 		,  		 			Oh 		.  		Feb.15-18 2009. p. .  		 			ICACT 		 	 
\bibitem[Coppola et al. (2012)]{b11}\label{b11} 	 		‘White paper on OCCN: A Network-On-Chip Modeling and Simulation Framework, ISD Integrated system developments, page 8. 11. Naveen Chaudhary, Bursty Communication Performance Analysis of Network-on-Chip with Diverse Traffic Permutations’.  		 			M Coppola 		,  		 			S Curaba 		,  		 			M Grammatikakis 		,  		 			R Locatelli 		,  		 			G Maruccia 		,  		 			F Papariello 		,  		 			L Pieralisi 		.  	 	 		\textit{International Journal of Soft Computing and Engineering (IJSCE)}  		 2231-2307.  		January 2012.  (1) .  	 
\bibitem[©2011 IEEE, A Tree-Based Topology Synthesis for On-Chip Network]{b6}\label{b6} 	 		 26.00.  		\textit{©2011 IEEE, A Tree-Based Topology Synthesis for On-Chip Network},  				p. .  	 
\end{bibitemlist}
 			 		 	 
\end{document}
